MICROCHLIP RTG4 Goddefgarwch Ymbelydredd Cenhedlaeth 4
RHAGARWEINIAD
Mae'r Nodyn Cais hwn yn disgrifio amrywiol ffynonellau cloc a chylchedau rhyngwyneb Vectron y gellir eu defnyddio i yrru Mewnbynnau'r Cloc Cyfeirio (REFCLK) o Flociau SerDes yr FPGA sy'n goddef ymbelydredd RTG4.
Gall y Microchip RTG4 (Radiation-Tolerant Generation4) FPGA (Field Programmable Gate Array) dderbyn signalau cloc mewn dau fath o fewnbynnau cloc:
- Clock signals into the RTG4 general purpose and dedicated clock input pins, for use as a clock to the logic in the Digital Fabric.
- Clock signals into the SerDes Blocks Reference Clock input pins, which input a reference clock for use by the dedicated high-speed SerDes Blocks on chip.
Of the two types of clock inputs, RTG4 REFCLK Inputs will be examined for this Application Note. The RTG4 REFCLK Inputs can be programmed by a FPGA designer to one of the various receiver types (differential or single-ended signal), and each has logic level requirements that will need direct interface or translation interface circuit connections to work properly when used with a standard clock driver (See Table 4). Information for providing clock input to the RTG4 Digital Fabric (type ‘1’ above) is not presented here, but it can be connected with a standard driver clock the same as providing clock input to the RTG4 REFCLK receivers.
Yn ogystal â rhestru a thrafod y dyfeisiau hyn, mae'r Nodyn Cais hwn hefyd yn crynhoi lefelau rhesymeg manyleb Mewnbynnau REFCLK RTG4 sy'n ofynnol ar gyfer gyrwyr ffynhonnell y cloc gyda lefelau rhesymeg allbwn a gyflwynir yn Nhabl 4. Mae'r Nodyn Cais hefyd yn dangos gosodiadau a mesuriadau gyda rhai tonffurfiau nodweddiadol a brofwyd yn y DevKit RTG4, er mwyn rhoi hyder bod yr atebion yn gweithio mewn caledwedd.
CLOCAU AR GYFER GYRRU MEWNBYNIADAU REFCLK FPGA RTG4
Mae'r nodyn cais hwn yn manylu ar y defnydd o gyfresi osgiliadur lluosog, y gylchedwaith gofynnol, a'r gosodiadau cyfatebol ar gyfer yr REFCLK RTG4. Mae Tabl 1 yn darparu cyfeirnod cyflym i gwsmeriaid ar gyfer rhifau rhannau osgiliadur y gellir eu harchebu ar amleddau cyffredin. Yr osgiliaduron a restrir yw CMOS pen sengl 2.5V neu 3.3V neu allbwn LVDS cyflenwol 3.3V, dos ïoneiddio cyfanswm lleiaf (TID) o 100 krad, a gellir eu cyplysu'n uniongyrchol â'r RTG4 gyda'r gosodiad LVCMOS25, LVCMOS33, neu LVDS25_ODT. Mae'r opsiynau cost isaf sy'n bodloni cydymffurfiaeth lawn ar gyfer lefelau sgrinio'r RTG4 wedi'u rhestru. Darperir gwybodaeth ar ôl Tabl 1 os oes angen ffurfweddiadau, lefelau ymbelydredd (hyd at 300 krad), neu gaeadau osgiliadur eraill. Darperir y wybodaeth ar ôl Tabl 1 hefyd at ddibenion cydymffurfio.
TABL 1: RECOMMENDED VECTRON HIGH RELIABILITY OSCILLATOR MODELS AT THREE PRIMARY REFERENCE CLOCK FREQUENCIES.
| Lefel Sgrinio FPGA | Prif Amledd y Cloc | Rhesymeg Allbwn | Rhif Model yr Osgilydd | Cyfeirnod Safonol Osgilydd Dibynadwyedd Uchel Vectron |
| ES, MS, Proto | 100 MHz | CMOS | 1157D100M0000BX | OS-68338 |
| B | 1157B100M0000BE | |||
| EV, V | 1157R100M0000BS | |||
| ES, MS, Proto | 100 MHz | LVDS | 1203D100M0000BX | DOC203679 |
| B | 1203B100M0000BE | |||
| EV, V | 1203R100M0000BS | |||
| ES, MS, Proto | 125 MHz | CMOS | 1403D125M0000BX | DOC204900 |
| 1403D125M0000CX | ||||
| B | 125 MHz | CMOS | 1403B125M0000BE | DOC204900 |
| 1403B125M0000CE | ||||
| EV | 125 MHz | CMOS | 1403R125M0000BS | DOC204900 |
| 1403R125M0000CS | ||||
| ES, MS, Proto | 125 MHz | LVDS | 1203D125M0000BX | DOC203679 |
| B | 1203B125M0000BE | |||
| EV, V | 1203R125M0000BS | |||
| ES, MS, Proto | 156.25 MHz | LVDS | 1203D156M2500BX | DOC203679 |
| B | 1203B156M2500BE | |||
| EV, V | 1203R156M2500BS |
Os oes angen amledd arall, allbwn rhesymeg, cyfaint cyflenwad ar raglentage, lefel TID, neu lloc osgiliadur, argymhellir defnyddio'r holl Safonau Osgiliadur Dibynadwyedd Uchel Vectron canlynol fel y REFCLK.
- LVDS (See Setup Figure 2 and Figure 4):
- LVPECL (See Setup Figure 7, Figure 9, and Figure 11):
- DOC203810, Oscillator Specification, Hybrid Clock for Hi-Rel Standard, LVPECL Output
- CMOS (See Figure 13):
- OS-68338, Oscillator Specification, Hybrid Clock, Hi-Rel Standard, CMOS Output (3.3V supply, 100 krad)
- DOC206379, Oscillator Specification, Hybrid Clock for Hi-Rel Standard, 300 krad Tolerant CMOS (3.3V supply, 300 krad)
- DOC204900, Oscillator Specification, Hybrid Clock for Hi-Rel Standard, High Frequency CMOS (2.5V/3.3V supply, 100 krad)
MEWNBYNIADAU REFCLK FPGA RTG4
Gellir ffurfweddu Mewnbynnau REFCLK RTG4, gan y dylunydd FPGA, i unrhyw un o'r Safonau IO a restrir isod (Cyfeiriad: Tabl 5 o Ganllaw Defnyddiwr UG0567, Rhyngwynebau Cyfresol Cyflymder Uchel RTG4 FPGA).
TABL 2: INPUT CONFIGURATION OPTIONS
| Cyflenwad SERDES_VDDI | 3.3V | 2.5V | 1.8V |
| Safonau a Gefnogir | LVTTL/LVCMOS33 | LVCMOS25 | LVCMOS18 |
| LVDS33 | LVDS25 (Nodyn 1) | SSTL18-Dosbarth 1 | |
| LVPECL | RSDS | SSTL18-Dosbarth 2 | |
| RSDS | Mini-LVDS | HSLT18-Dosbarth 1 | |
| Mini-LVDS | SSTL25-Dosbarth 1 | — | |
| — | SSTL25-Dosbarth 2 | — |
Nodyn
- Ar gyfer LVDS33 a LVDS25, dylai dylunwyr gyfeirio at Ganllaw Defnyddwyr RGT4 I/O a thaflen ddata DS0131 RTG4 FPGA am argymhellion terfynu a modd cyffredin cywir i gyflawni perfformiad jitter gorau posibl.
- Cefnogir mewnbynnau HCSL yn uniongyrchol gyda mewnbynnau LVDS I/O STD o'r Libero. Nid oes STD HCSL I/O penodol ar gael yn Libero a chefnogir dyluniadau sy'n gofyn am HCSL trwy ddefnyddio'r safon LVDS25 I/O.
Bydd rhaglennu'r Safon Mewnbwn/Allbwn hefyd yn gosod y math Mewnbynnau REFCLK cyfatebol. Cyflwynir y Mewnbynnau REFCLK poblogaidd canlynol yn y Nodyn Cais hwn gydag argymhellion:
- LVDS25_ODT: ODT improves the signaling environment by reducing the electrical discontinuities introduced with off-die termination; thus, it enables reliable operation at higher signaling rates (Microchip_RTG4_FPGA_IO_user_Guide_UG0741_V4). This also provides the common-mode noise rejection on the transmission lines all the way to the receiver with the built-in ODT to reduce noise emission and noise interferences. An LVDS or LVPECL clock (interface circuit needed) can be used to drive the LVDS25_ODT.
- LVDS25: It is recommended to use LVDS25_ODT for best waveform and jitter performance. When LVDS25 is used an external differential termination is required. An external differential termination resistor of 200Ω (typical) may be implemented to improve the VID minimum requirement margin when using with a standard LVDS driver.
The 200Ω load must be placed as close as possible to the RTG4 receiver input pins for better waveform and jitter performance. - LVDS33: This is not recommended for use due to the minimum VID requirement of 0.50V, which is higher than a standard LVDS output differential voltage o 0.34V ac mae hefyd yn uwch na'r gwahaniaeth allbwn LVPECL lleiaftage o 0.470V yn ôl Tabl 4.
- LVPECL33: This is not recommended for use due to the VICM requirement of 1.8V maximum, which is lower than the standard LVPECL output common mode voltage o 2.0V, ac oherwydd y gofyniad VID o leiaf 0.600V, sy'n uwch na'r gwahaniaeth allbwn LVPECL lleiaftage o 0.470V yn ôl Tabl 4.
- LVCMOS33/LVCMOS25: This is recommended for use. These are single-ended REFCLK Inputs, requiring no interface translating circuit for simple direct connections to reduce component count. OS-68338 3.3V clock up to 100 MHz can be used for driving LVCMOS33. The 300 krad DOC206379 3.3V clock up to 80 MHz can be used for driving LVCMOS33. For faster speed, the high frequency 2.5V/3.3V CMOS clock of DOC204900 up to 125 MHz can be used for driving LVCMOS25 (used with 2.5V clock) or LVCMOS33 (used with 3.3V clock). The max operating frequency of the high frequency CMOS DOC204900 is 160 MHz, but the application is limited to 125 MHz due to the high input capacitance 20 pF max of the RTG4 receiver. This application limit is based on the output sink/ source current capability of the oscillator clocks and the capacitive load (20 pF in this case), using the power dissipation formula.
Cyfrifir y Defnydd Pŵer Llwyth Capasitif drwy'r hafaliad canlynol.
HAFALIAD 1:
Lle:
C = The load capacitance.
f = The signal frequency.
IC = The dynamic consumption current.
P=C x V CC₂ x f=V CC x I C
I C =C x V CC x f
Am gynamph.y., ar 125 MHz a chyflenwad 3.0V, cyfrifir y cerrynt defnydd fel 20 pF x 3.0V x 125 MHz = 7.5 mA, fel y disgwylir iddo fod yn is na'r cerrynt sinc/ffynhonnell a argymhellir o 12 mA (Cyfeiriad: TI 54AC00-SP, byffer allbwn a ddefnyddir yn yr osgiliadur DOC204900).
CYFROL MEWNBWN RTG4 REFCLKTAGMANYLEBAU E A DATA ALLBWN Y GYRRWR
Mae'r mewnbwn cyftagRhestrir gofynion Mewnbynnau REFCLK RTG4 yn Nhabl 3 i ddarparu'r terfynau manyleb i ddata allbwn y gyrrwr a gyflwynir yn Nhabl 4.
TABL 3: RTG4 SERDES REFCLK INPUT VOLTAGMANYLEBAU E (Nodyn 1)
| COFIO Mewnbwn | Cyflenwad Cyftage (VDDI) |
VID (Nodyn 2) |
VICM (Nodyn 2) |
||||
| Minnau. | Teip. | Max. | Minnau. | Teip. | Max. | ||
| LVDS25_ODT | 2.5V ±5% | 0.20V | 0.35V | 2.40V | 0.05V | 1.25V | 1.50V |
| LVDS25 | 2.5V ±5% | 0.20V | 0.35V | 2.40V | 0.05V | 1.25V | 2.20V |
| LVDS33 (Nodyn 3) | 3.3V ±5% | 0.50V | — | 2.40V | 0.60V | 1.25V | 1.80V |
| LVPECL33 (Nodyn 3) | 3.3V ±5% | 0.60V | — | 2.40V | 0.60V | — | 1.80V |
|
— |
VIL |
VIH |
|||||
| LVCMOS25 | 2.5V ±5% | -0.30V | — | 0.70V | 1.7V | — | 2.625V |
| LVCMOS33 | 3.3V ±5% | -0.30V | — | 0.80V | 2.0V | — | 3.450V |
Nodyn
- See Microchip RTG4_FPGA data sheet for more details on SerDes REFCLK Input VoltagManylebau e.
- Figure 1 depicts the VID and VICM for the differential inputs. Note that VID is half of VDiff, and is equivalent to a single-ended signal referenced from one input to ground.
- Do not use LVDS33 and LVPECL33 as explained in the RTG4 FPGA REFCLK INPUTS section for LVDS33 and LVPECL33. These specification limits compared with the output data ranges in Table 4 are used to support this conclusion.
FFIGUR 1: VID a VICM ar gyfer Mewnbynnau Gwahaniaethol.
Hefyd, mae'n rhaid i'r VICM a'r VID fodloni amodau'r fformwlâu isod:
HAFALIAD 2:
VICM + (V ID/2)< VDDI + 0.4V
a
VICM- (VID/2)>–0.3V
TABL 4: CLOCK DRIVER INTERFACE CONFIGURATION AND OUTPUT DATA (Note 1)
| Ffigur Gosod | Cyfluniad Rhyngwyneb | VID (Nodyn 2) | VICM (Nodyn 2) | ||||
| Minnau. | Teip. | Max. | Minnau. | Teip. | Max. | ||
| Ffigur 2 (Nodyn 3) | LVDS to LVDS25_ODT Direct Interface | 0.250V | 0.340V | 0.450V | 1.125V | 1.250V | 1.450V |
| Ffigur 4 (Nodyn 4) | LVDS to LVDS25 200Ω Termination | 0.520V | 0.610V | 0.720V | 1.125V | 1.350V | 1.500V |
| Ffigur 7 (Nodyn 5) | LVPECL to LVDS25_ODT VICM 3.3V-Bias | 0.470V | 0.800V | 0.950V | Nodyn 5 | 1.240V | Nodyn 5 |
| Ffigur 9 (Nodyn 6) | LVPECL to LVDS25_ODT VICM Self-Bias | 0.470V | 0.800V | 0.950V | 1.030V | 1.233V | 1.437V |
| Ffigur 11 (Nodyn 7) | LVPECL to LVDS25_ODT VICM Self-Bias2 | 0.289V | 0.493V | 0.586V | 1.030V | 1.233V | 1.437V |
|
— |
VIL |
VIH |
|||||
| Ffigur 13 (Nodyn 8) | CMOS i LVCMOS33 | 0.297V | 0.330V | 0.363V | 2.673V | 2.970V | 3.267V |
| (Nodyn 8) | CMOS i LVCMOS25 | 0.237V | 0.250V | 0.263V | 2.138V | 2.250V | 2.363V |
Nodyn
- Output Data is recorded as VID and VICM to be consistent with the RTG4 REFCLK Inputs Voltagcyfeiriadau e. Gweler y Ffigurau Gosod a'r tonffurfiau canlyniadol am fanylion ar ddefnydd ffynhonnell y cloc a chylchedau rhyngwyneb. Gweler hefyd yr adran Mesuriadau Jitter am wybodaeth ychwanegol.
- VID and VICM are referenced to Ground. VID is a single-ended signal measured at the input of the RTG4 receiver to correspond with the specification VID of the RTG4 REFCLK Inputs (see Note 2 of Table 3). All the logic levels also meet the conditions of the formulas required for the RTG4 REFCLK Inputs: VICM + (VID/2) < VDDI + 0.4V and VICM – (VID/2) > –0.3V.
- Setup Figure 2: The VID and VICM limits are defined by the output voltaglefelau e o Dabl 2 o Vectron
DOC203679 for standard LVDS. - Setup Figure 4: The typical values of VID and VICM are determined by measurements.
- Setup Figure 7: The VID range is determined using the output voltaglefelau e o Dabl 2 o Vectron DOC203810, “Cyfaint Allbwntage: VOH = VCC – 1.085 to VCC – 0.880, VOL = VCC – 1.830 to VCC – 1.555”.
The biasing network resistors (R3 to R6) and its supply voltage fydd yn pennu'r ystod VICM ar gyfer y cynllun hwn. - Setup Figure 9: The VID range is determined using the output voltaglefelau e o Dabl 2 o Vectron DOC203810, “Cyfaint Allbwntage: VOH = VCC – 1.085 to VCC – 0.880, VOL = VCC – 1.830 to VCC – 1.555”.
The LVPECL output common mode voltage is calculated as VCC – 1.3V. With a VCC of 3.3V ±10%, the VICM ranges from 1.030V to 1.437V for this interface scheme with the resistor nominal values. - Setup Figure 11: The VID range is determined using the output voltaglefelau e o Dabl 2 o Vectron
DOC203810, “Cyfaint Allbwntage: VOH = VCC – 1.085 to VCC – 0.880, VOL = VCC – 1.830 to VCC – 1.555”, and through the voltage divider, the 51Ω and 82Ω resistor network. The LVPECL output common mode voltage is calculated as VCC – 1.3V. With a VCC of 3.3V ±10%, the VICM ranges from 1.030V to 1.437V for this interface scheme with the resistor nominal values. - Setup Figure 13: The VIL and VIH range is determined by the standard CMOS logic levels as VIL = VCC x 0.1 and VIH = VCC x 0.9, where VCC is the supply voltage 3.3V ±10% neu 2.5V ±5%.
CYMHARU LEFELAU SGRINIAU RTG4 YN ERBYN SGRINIAU OSGILATOR A PHEDIGRIAU
Oherwydd gwahaniaethau yn y gofynion a restrir yn MIL-PRF-38535 (ar gyfer electroneg wedi'i galedu gan ymbelydredd) a MIL-PRF55310 (ar gyfer osgiliaduron crisial), nid oes cyfatebiaethau union mewn lefelau sgrinio a phedairi cydrannau ar gael. Mae Tabl 5 yn crynhoi lefelau sgrinio ar gyfer yr RTG4, a'r lefelau sgrinio a phedairi cyfatebol a argymhellir ar gyfer Osgiliaduron Vectron. Anogir cwsmeriaid i ail-view manylebau perthnasol ar gyfer cymwysiadau hollbwysig i sicrhau cydymffurfiaeth lawn.
TABL 5: RTG4 SCREENING LEVELS VS. OSCILLATOR SCREENING AND PEDIGREES
| RTG4 Sgrinio Lefel | Sgrinio Osgiliadur | Oscillator Component Pedigree | Disgrifiad |
| ES, MS, Proto | X | D | Engineering Model Hardware using high reliability design with com- metrical grade components and non-swept quartz. |
| B | E | B | Caledwedd Gradd Filwrol gan ddefnyddio dyluniad dibynadwyedd uchel gyda chydrannau gradd milwrol a chwarts wedi'i ysgubo. |
| EV, V | S | R | Caledwedd Gradd Gofod gyda marw 100 krad, cydrannau gradd gofod, a chwarts wedi'i ysgubo. |
GENERAL RECOMMENDATIONS AND SUMMARY
- When an external resistor like the 200Ω termination for differential driving is used, it must be placed as close as possible to the differential receiver input pins. Otherwise, waveform and jitter will greatly degrade.
- RTG4 differential receiver must be terminated at the inputs either with an external resistor (100Ω or 200Ω) or with ODT (RTG4 On-Die Termination) for all clock driver types for best waveform and jitter performance.
- The clock oscillator driver should be placed as close as possible to the input pins of the RTG4 receiver to help reduce interferences and minimize reflection on the transmission line due to possible impedance mismatching.
- It is recommended to use the drivers and interface circuits listed in Table 4. Do not use the RTG4 REFCLK Inputs LVDS33 and LVPECL33.
TABL 6: RTG4 REFCLK INPUTS AND CLOCK DRIVER MATRIX
| Math o Arwydd | RTG4 |
Gyrrwr Cloc Vectron |
|||||
| Mewnbwn REFCLK | Math o Gloc | Lluniad Manyleb | Radiation Tolerance | Cyflenwad Cyftage | Max. Amlder | Cylchdaith Terfynu | |
| Gwahaniaethol | LVDS25_ODT | LVDS | DOC203679 | 100 krad | 3.3V | 200 MHz | Rhyngwyneb Uniongyrchol Ffigur 2 |
| DOC206903 | 300 krad | 3.3V | 200 MHz | ||||
| LVDS25_ODT | LVPECL | DOC203810 | 50 krad (ELDRS) | 3.3V | 700 MHz | Ffigur 7, Ffigur 9, Ffigur 11 | |
| LVDS25 | LVDS | DOC203679 | 100 krad | 3.3V | 200 MHz | 200Ω, Ffigur 4 | |
| DOC206903 | 300 krad | 3.3V | 200 MHz | ||||
| LVDS33 |
Peidiwch â Defnyddio |
||||||
| LVPECL33 |
Peidiwch â Defnyddio |
||||||
| Diwedd Sengl | LVCMOS33 | CMOS | OS-68338 | 100 krad | 3.3V | 100 MHz | Rhyngwyneb Uniongyrchol Ffigur 13 |
| DOC204900 | 100 krad | 3.3V | 125 MHz | ||||
| DOC206379 | 300 krad | 3.3V | 80 MHz | ||||
| LVCMOS25 | CMOS | DOC204900 | 100 krad | 2.5V | 125 MHz | Rhyngwyneb Uniongyrchol Ffigur 13 | |
For differential signal application, the only choice for RTG4 to set to is LVDS25_ODT (used with LVDS or LVPECL clock driver) or LVDS25 (used with LVDS clock driver and external 200Ω termination). The CMOS single-ended signal solution offers the best Total Jitter and Deterministic Jitter performance (See Jitter Measurements Table 7, Table 8, and Table 9), simple direct interface and options to use either the 2.5V or 3.3V supply, but speed is limited to 100 MHz (OS-68338), 80 MHz (DOC206379) and 125 MHz (DOC204900) for the three Vectron CMOS clocks.
RHYNGWYNEB CYLCH A DATA
FFIGUR 2: LVDS i RTG4 LVDS25_ODT, Rhyngwyneb Uniongyrchol.
FFIGUR 3: Measured Waveforms, LVDS to LVDS25_ODT, Direct Interface (Waveforms Measured on RTG4 DevKit).
Nodyn
- A LeCroy active probe ZS1500 1.5 GHz was used for the measurements. VID1 and VID2 were measured with reference to Ground at room temperature.
- See Figure 2 for the setup diagram. The oscillator clock driver (1204R156M25000BF used) was mounted on the RTG4 DevKit in place of the REFCLK 125 MHz (disabled and isolated) and the whole board was tested over temperature from –40°C to +85°C with Microchip EPCS Demo GUI software used to check for the error-free transmission loop.
FFIGUR 4: LVDS to RTG4 LVDS25 External 200Ω Termination.
FFIGUR 5: Setup Diagram for LVDS 200Ω Termination.
Nodyn
- This test setup was used to measure the waveforms for the diagram Figure 4 to present here in place of the waveforms measured on the RTG4 DevKit. The waveforms measured on the DevKit using the setup of Figure 4 were not so representative because the 200Ω load resistor used with the RTG4 LVDS25 couldn’t be placed as close to the receiver inputs as recommended to obtain good waveforms.
- The load was placed at the input of the oscilloscope for better waveform measurements. Only half of the signal was measured using this setup. The 50Ω series resistors connected via the oscilloscope ground form a load of 200Ω between two outputs of the LVDS oscillator. The clock source used was 1204R156M25000BF.
FFIGUR 6: Measured Waveforms, LVDS to LVDS25, External 200Ω Termination (Waveforms Measured with Bench Fixture and 50Ω Coax Cables).
Nodyn
- The actual signal is two times the measured value, as explained in Figure 5. Waveform was measured at room temperature.
FFIGUR 7: LVPECL i LVDS25_ODT, VICM 3.3V-Bias.
Nodyn
- Use 1 kΩ for R4 and R6 if a supply voltage of 2.5V is used for the biasing network.
- C1 and C2 of 0.1 µF not only serve as a DC block, but also provide a full LVPECL differential signal swing to drive the receiver with little attenuation. The AC-coupling capacitors should have low ESR and low inductance at targeted clock frequency.
FFIGUR 8: Measured Waveforms, LVPECL to LVDS25_ODT, VICM 3.3V-Bias (Waveforms Measured on RTG4 DevKit).
Nodyn
- A LeCroy active probe ZS1500 1.5 GHz was used for the measurements. VID1 and VID2 were measured with reference to Ground at room temperature.
- See Figure 7 for the setup diagram. The oscillator clock driver (1304R156M25000BF used) was mounted on the RTG4 DevKit in place of the REFCLK 125 MHz (disabled and isolated) for testing.
FFIGUR 9: LVPECL to LVDS25_ODT, V ICM Self-Bias.
Nodyn
- This VICM Self-Bias Termination is an alternative to that of Figure 7. This scheme requires no external supply voltage for the biasing and saves two resistors over that of Figure 7.
- C1 and C2 of 0.1 µF provide a full LVPECL differential signal swing to drive the receiver with little attenuation. The AC-coupling capacitors should have low ESR and low inductance at targeted clock frequency.
FFIGUR 10: Measured Waveforms, LVPECL to LVDS25_ODT, VICM Self-Bias (Waveforms Measured on RTG4 DevKit).
Nodyn
- A LeCroy active probe ZS1500 1.5 GHz was used for the measurements. VID1 and VID2 were measured with reference to Ground at room temperature.
- See Figure 9 for the setup diagram. The oscillator clock driver (1304R156M25000BF used) was mounted on the RTG4 DevKit in place of the REFCLK 125 MHz (disabled and isolated) for testing.
FFIGUR 11: LVPECL i LVDS_ODT, VICM Hunan-Rhagfarn2.
Nodyn
- This VICM Self-Bias termination is similar to the setup of Figure 9 without the coupling capacitors C1 and C2. The driver output signal is divided down by the resistor network but is still large enough to drive the RTG4 LVDS25_ODT. The rad-hard oscillator 1304R156M25000BF can be used for the clock source.
FFIGUR 12: Simulated Waveforms, LVPECL to LVDS25_ODT, VICM Self-Bias2 (Keysight ADS 2017 software used).
IGURE 13: CMOS i RTG4 LVCMOS33.
Nodyn
- A Vectron OS-68338 1103R100M00000BF 3.3V CMOS clock was used in the setup to drive the RTG4 LVCMOS33 and the waveform at Q was measured and presented in Figure 14.
FFIGUR 14: Tonffurfiau wedi'u Mesur, CLOC CMOS (OS-68338 100 MHz) i LVCMOS33.
Nodyn
- A LeCroy active probe ZS1500 1.5 GHz was used for the measurement. The waveform was measured at the output of the clock driver at room temperature.
- See Figure 13 for the setup diagram. The oscillator clock driver (1103R100M00000BF used) was mounted on the RTG4 DevKit in place of the REFCLK 125 MHz (disabled and isolated) for testing.
MESURIADAU JITTER
O fewn pob trosglwyddydd o'r SerDes, mae'r sylfaen amser a ddarperir gan y cloc cyfeirio i'r TXPLL yn effeithio'n uniongyrchol ar ansawdd data allbwn cyfresol y SerDes. Bydd yr amrywiadau jitter a chyfnod sy'n bresennol ar y cloc cyfeirio y mae'r TXPLL yn ei dderbyn hefyd yn ymddangos ar y ffrwd ddata cyfresol cyflym y mae'n ei chynhyrchu. Mae'r data canlynol yn cynrychioli cynnwys jitter y data cyfresol cyflym o'r SerDes gan ddefnyddio'r gwahanol gynlluniau cloc cyfeirio. Mae'r data isod yn dangos ansawdd ffrwd ddata PRBS7 3.125 Gbps a drosglwyddir gyda'r atebion cloc cyfeirio a drafodwyd.
FFIGUR 15: Data Jitter, LVDS i LVDS25_ODT, Rhyngwyneb Uniongyrchol (Ffigur Gosod 2).
FFIGUR 16: Diagram Llygad, LVDS i LVDS25_ODT, Rhyngwyneb Uniongyrchol (Ffigur Gosod 2).
FFIGUR 17: Jitter Data, LVDS to LVDS25 200Ω External Termination (Setup Figure 4).
FFIGUR 18: Eye Diagram, LVDS to LVDS25 200Ω External Termination (Setup Figure 4).
FFIGUR 19: Data Jitter, LVPECL i LVDS25_ODT (Ffigur Gosod 9).
FFIGUR 20: Diagram Llygad, LVPECL i LVDS25_ODT (Ffigur Gosod 9).
Mae'r tablau canlynol yn cyflwyno'r astudiaeth a wnaed gan dîm nodweddu Microsemi, gan gymharu jitter trosglwyddo SerDes â gwahanol fathau o RefClk.
TABL 7: JITTER DATA, RTG4 SERDES OUTPUT AT 3.125 GBPS FOR ALL REFCLK STANDARDS.
| Rhif Dyfais | Temp. | Cyftage Cyflwr | Paramedr | LVDS 2.5V | LVCMOS 2.5V | LVCMOS 3.3V | SSTL 1.8V | SSTL 2.5V | HSTL 1.8V |
| 902 | 125°C | Minnau. | Total Jitter (mUI) | 318 | 309 | 306 | 481 | 371 | 445 |
| Jitter Penderfynol (mUI) | 257 | 266 | 265 | 438 | 328 | 403 | |||
| 25°C | Teip. | Total Jitter (mUI) | 343 | 289 | 287 | 355 | 406 | 358 | |
| Jitter Penderfynol (mUI) | 291 | 246 | 247 | 315 | 366 | 318 | |||
| –55 ° C. | Max. | Total Jitter (mUI) | 257 | 263 | 273 | 340 | 458 | 316 | |
| Jitter Penderfynol (mUI) | 221 | 222 | 232 | 304 | 414 | 275 | |||
| 905 | 125°C | Minnau. | Total Jitter (mUI) | 309 | 304 | 301 | 429 | 362 | 453 |
| Jitter Penderfynol (mUI) | 250 | 263 | 259 | 386 | 317 | 409 | |||
| 25°C | Teip. | Total Jitter (mUI) | 325 | 287 | 286 | 371 | 458 | 364 | |
| Jitter Penderfynol (mUI) | 275 | 251 | 246 | 334 | 422 | 326 | |||
| –55 ° C. | Max. | Total Jitter (mUI) | 336 | 265 | 277 | 307 | 423 | 320 | |
| Jitter Penderfynol (mUI) | 297 | 226 | 237 | 270 | 381 | 278 | |||
| 911 | 125°C | Minnau. | Total Jitter (mUI) | 350 | 320 | 294 | 402 | 435 | 435 |
| Jitter Penderfynol (mUI) | 286 | 276 | 250 | 357 | 391 | 390 | |||
| 25°C | Teip. | Total Jitter (mUI) | 332 | 303 | 301 | 427 | 451 | 333 | |
| Jitter Penderfynol (mUI) | 273 | 257 | 253 | 384 | 407 | 291 | |||
| –55 ° C. | Max. | Total Jitter (mUI) | 320 | 277 | 264 | 312 | 385 | 331 | |
| Jitter Penderfynol (mUI) | 278 | 239 | 223 | 271 | 342 | 293 |
TABL 8: JITTER DATA, RTG4 SERDES OUTPUT AT 2.5 GBPS FOR ALL REFCLK STANDARDS.
| Rhif Dyfais | Temp. | Cyftage Cyflwr | Paramedr | LVDS 2.5V | LVCMOS 2.5V | LVCMOS 3.3V | SSTL 1.8V | SSTL 2.5V | HSTL 1.8V |
| 902 | 125°C | Minnau. | Total Jitter (mUI) | 202 | 164 | 168 | 188 | 188 | 224 |
| Jitter Penderfynol (mUI) | 164 | 135 | 129 | 157 | 159 | 216 | |||
| 25°C | Teip. | Total Jitter (mUI) | 200 | 143 | 146 | 181 | 214 | 241 | |
| Jitter Penderfynol (mUI) | 170 | 117 | 120 | 151 | 185 | 213 | |||
| –55 ° C. | Max. | Total Jitter (mUI) | 169 | 161 | 148 | 186 | 186 | 231 | |
| Jitter Penderfynol (mUI) | 136 | 135 | 122 | 159 | 159 | 168 | |||
| 905 | 125°C | Minnau. | Total Jitter (mUI) | 174 | 165 | 167 | 187 | 194 | 217 |
| Jitter Penderfynol (mUI) | 146 | 131 | 136 | 153 | 166 | 190 | |||
| 25°C | Teip. | Total Jitter (mUI) | 189 | 144 | 147 | 173 | 190 | 242 | |
| Jitter Penderfynol (mUI) | 163 | 118 | 118 | 147 | 161 | 196 | |||
| –55 ° C. | Max. | Total Jitter (mUI) | 157 | 152 | 146 | 190 | 187 | 229 | |
| Jitter Penderfynol (mUI) | 130 | 127 | 120 | 161 | 158 | 156 | |||
| 911 | 125°C | Minnau. | Total Jitter (mUI) | 193 | 185 | 184 | 200 | 223 | 252 |
| Jitter Penderfynol (mUI) | 166 | 151 | 147 | 169 | 177 | 190 | |||
| 25°C | Teip. | Total Jitter (mUI) | 182 | 163 | 175 | 197 | 196 | 215 | |
| Jitter Penderfynol (mUI) | 151 | 131 | 143 | 164 | 163 | 159 | |||
| –55 ° C. | Max. | Total Jitter (mUI) | 159 | 145 | 150 | 208 | 199 | 182 | |
| Jitter Penderfynol (mUI) | 134 | 119 | 118 | 166 | 169 | 155 |
TABL 9: JITTER DATA, RTG4 SERDES OUTPUT AT 1.25 GBPS FOR ALL REFCLK STANDARDS.
| Rhif Dyfais | Temp. | Cyftage Cyflwr | Paramedr | LVDS 2.5V | LVCMOS 2.5V | LVCMOS 3.3V | SSTL 1.8V | SSTL 2.5V | HSTL 1.8V |
| 902 | 125°C | Minnau. | Total Jitter (mUI) | 92 | 106 | 99 | 134 | 95 | 114 |
| Jitter Penderfynol (mUI) | 73 | 85 | 80 | 114 | 66 | 91 | |||
| 25°C | Teip. | Total Jitter (mUI) | 100 | 99 | 99 | 88 | 99 | 108 | |
| Jitter Penderfynol (mUI) | 16 | 77 | 76 | 68 | 76 | 79 | |||
| –55 ° C. | Max. | Total Jitter (mUI) | 97 | 93 | 94 | 114 | 91 | 106 | |
| Jitter Penderfynol (mUI) | 78 | 73 | 72 | 90 | 65 | 84 | |||
| 905 | 125°C | Minnau. | Total Jitter (mUI) | 100 | 100 | 106 | 97 | 122 | 130 |
| Jitter Penderfynol (mUI) | 76 | 74 | 87 | 69 | 90 | 101 | |||
| 25°C | Teip. | Total Jitter (mUI) | 90 | 97 | 104 | 103 | 103 | 99 | |
| Jitter Penderfynol (mUI) | 66 | 70 | 83 | 79 | 80 | 77 | |||
| –55 ° C. | Max. | Total Jitter (mUI) | 98 | 87 | 91 | 115 | 98 | 100 | |
| Jitter Penderfynol (mUI) | 79 | 67 | 70 | 93 | 71 | 74 | |||
| 911 | 125°C | Minnau. | Total Jitter (mUI) | 82 | 108 | 117 | 137 | 730 | 155 |
| Jitter Penderfynol (mUI) | 65 | 79 | 97 | 105 | 101 | 107 | |||
| 25°C | Teip. | Total Jitter (mUI) | 115 | 115 | 776 | 108 | 110 | 146 | |
| Jitter Penderfynol (mUI) | 90 | 83 | 85 | 72 | 82 | 116 | |||
| –55 ° C. | Max. | Total Jitter (mUI) | 99 | 96 | 104 | 111 | 117 | 91 | |
| Jitter Penderfynol (mUI) | 75 | 78 | 81 | 78 | 90 | 62 |
Offer Caledwedd a Meddalwedd a Ddefnyddiwyd
The RTG4 Development Kit was used for testing the reference clocks and for waveform measurements. The RTG4 Development Kits on-board REFCLK CCLD-033-50-125.000 oscillator was disabled, isolated, and replaced with the Vectron clock driver LVPECL or LVDS along with the interface circuit for each testing of the clock types. Also, in-house test fixtures were developed for the specific tests of LVDS with a 200Ω load.
Defnyddiwyd Meddalwedd Microchip Libero SoC V11.9 i raglennu'r Pecynnau Datblygu RTG4, llwytho dyluniadau prosiect a gosod y math derbynnydd Mewnbwn SerDes REFCLK i'w brofi gyda'r cloc cyfatebol. Defnyddiwyd GUI Demo EPCS Microchip i wirio ansawdd y signal trwy brofi'r ddolen ddata ddi-wall rhwng trosglwyddydd RTG4 a derbynnydd y bloc SerDes, a hefyd i wirio'r cysylltiadau cylched cloc yn y bwrdd datblygu RTG4.
Keysight ADS 2017 was used to generate circuit diagrams and for simulations when needed; IBIS models used in the simulations were Microsemi RTG4 REFCLK Receiver rt4g_msio.ibs, Michel Semiconductor ibisTop_100el16 in sc07p07el0160a, Aero flex/Chobham ut54lvds031lvucc.ibs, and Fairchild ACT3301 cgs3311m 3_3V.ibs.
- Microchip Hi-Rel Clock Oscillator Landing Page: Space Oscillators
- Microchip RTG4 Radiation-Tolerant FPGAs: https://www.microsemi.com/product-directory/rad-tolerant-fpgas/
3576-rtg4#documents - Microchip DS0131 Data Sheet RTG4 FPGA: https://www.microsemi.com/document-portal/doc_view/135193-
ds0131-rtg4-fpga-datasheet - Microchip RTG4 Development Kits: https://www.microsemi.com/product-directory/dev-kits-solutions/3865-rtg4-kits
- Microchip DG0624 Demo Guide RTG4 FPGA SerDes EPCS Protocol Design: https://www.microsemi.com/document-portal/doc_download/135196-dg0624-rtg4-fpga-serdes-epcs-protocol-design-libero-soc-v11-9-sp1-demoguide
- Microchip UG0567, RTG4 FPGA High Speed Serial Interfaces User Guide: https://www.microsemi.com/document-portal/doc_download/134409-ug0567-rtg4-fpga-high-speed-serial-interfaces-user-guide
- Microchip SY100EL16V: https://www.microchip.com/wwwproducts/en/SY100EL16V
- Front grade Technologies, UT54LVDS031LV/E Quad Driver: https://www.frontgrade.com/sites/default/files/documents/Datasheet-UT54LVDS031LVE.pdf
- Keysight Technologies, Advanced Design Systems (ADS): https://www.keysight.com/en/pc-1297113/advanced-design-system-adscc=US&lc=eng
- TI SN54AC00-SP Radiation Hardened Quad 2 Input NAND Gate: http://www.ti.com/lit/ds/symlink/sn54ac00-sp.pdf
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